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R. Sampson

High performance UTBB FDSOI devices featuring 20nm gate length for 14nm node and beyond
2013 · Q. Liu, M. Vinet, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 106
A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI
2014 · K. -I. Seo, B. Haran, et al. · Symposium on VLSI Technology · 103
Ultra-thin-body and BOX (UTBB) fully depleted (FD) device integration for 22nm node and beyond
2010 · Q. Liu, A. Yagishita, et al. · Symposium on VLSI Technology · 91
High performance extremely thin SOI (ETSOI) hybrid CMOS with Si channel NFET and strained SiGe channel PFET
2012 · K. Cheng, A. Khakifirooz, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 85
Competitive and cost effective high-k based 28nm CMOS technology for low power applications
2009 · F. Arnaud, A. Thean, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 56
UTBB FDSOI scaling enablers for the 10nm node
2013 · L. Grenouillet, Q. Liu, et al. · IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference · 34
A mobility enhancement strategy for sub-14nm power-efficient FDSOI technologies
2014 · B. DeSalvo, P. Morin, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 32
FDSOI CMOS devices featuring dual strained channel and thin BOX extendable to the 10nm node
2014 · Q. Liu, B. DeSalvo, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 31
High performance bulk planar 20nm CMOS technology for low power mobile applications
2012 · Huiling Shang, S. Jain, et al. · Symposium on VLSI Technology · 29
Bottom oxidation through STI (BOTS) — A novel approach to fabricate dielectric isolated FinFETs on bulk substrates
2014 · K. Cheng, S. Seo, et al. · Symposium on VLSI Technology · 19
New layout dependency in high-k/Metal Gate MOSFETs
2011 · M. Hamaguchi, D. Nair, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 14
10nm FINFET technology for low power and high performance applications
2014 · D. Guo, H. Shang, et al. · IEEE International Conference on Solid-State and Integrated Circuit Technology · 10
Performance elements for 28nm gate length bulk devices with gate first high-k metal gate
2010 · J. Yuan, C. Gruensfelder, et al. · IEEE International Conference on Solid-State and Integrated Circuit Technology · 4
64nm pitch interconnects: Optimized for designability, manufacturability and extendibility
2013 · Cindy Goldberg, S. H. Park, et al. · 3
Competitive and cost effective copper/low-k interconnect (BEOL) for 28nm CMOS technologies
2011 · R. Augur, C. Child, et al. · Microelectronic Engineering · 3
Raised S/D for Advanced Planar MOSFET devices: Challenges and Applications for the 20nm Node and Beyond
2010 · N. Loubet, P. Khare, et al. · International Conference on Solid State Devices and Materials (SSDM) · 1
Advanced Low Temperature Raised S/D Epitaxy Using Cyclic and Poly-Selective Techniques
2009 · N. Loubet, P. Khare, et al. · International Conference on Solid State Devices and Materials (SSDM) · 1
Design and optimization of a buried channel PMOS integrable in a Si1−xGex BiCMOS process
2007 · P. Khare, D. Schroder, et al. · Solid-State Electronics · 1
Cost Efficient Novel High Performance Analog Devices Integrated with Advanced HKMG Scheme for 28nm CMOS Technology and Beyond
2010 · J. P. Han, T. Shimizu, et al. · International Conference on Solid State Devices and Materials (SSDM)
A Comprehensive Modeling of MOS Transistors in a 0.35um Technology for Analog and Digital Applications
2002 · A.A. Keshavarz, Prasanna Khare, et al. · TechConnect Briefs
Mobility Degradation and Current Loss Due to Vertical Electric Field in Channel Area of Submicron MOS Devices
2000 · A.A. Keshavarz, R. Sampson, et al. · TechConnect Briefs
Works count: 21
Citation count: 623
H-index: 11
I10-index: 12
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