Keyword

VLSI testing

Description: Methods for detecting defects and verifying the operation of very-large-scale integrated circuits during design, manufacture, and use.

Primary topic: VLSI and Analog Circuit Testing (85%)

OpenAlex ID: keywords/vlsi-testing

Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits

2002 · Michael L. Bushnell, Vishwani D. Agrawal · Frontiers in electronic testing · 1,519

Built-in test for VLSI: Pseudorandom techniques

1989 · Integration · 862

Built-in test for VLSI — pseudorandom techniques

1989 · Colin Maunder · Microprocessors and Microsystems · 638

A distributed BIST control scheme for complex VLSI devices

2002 · Y. Zorian · Proceedings - IEEE VLSI Test Symposium/Proceedings of the ... IEEE VLSI Test Symposium · 538

VLSI Test Principles and Architectures: Design for Testability

2006 · Laung‐Terng Wang, Cheng‐Wen Wu, et al. · 445

Transition Fault Simulation

1987 · John Waicukauski, Eric Lindbloom, et al. · IEEE Design & Test of Computers · 402

Scheduling tests for VLSI systems under power constraints

1997 · R.M. Chou, K.K. Saluja, et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 289

Failure diagnosis of structured VLSI

1989 · J.A. Waicukauski, E. Lindbloom · IEEE Design & Test of Computers · 283

On-Line Testing for VLSI—A Compendium of Approaches

1998 · M. Nicolaidis, Y. Zorian · Journal of Electronic Testing · 246

Realistic fault modeling for VLSI testing

1987 · W. Maly · Proceedings - ACM IEEE Design Automation Conference · 241

Built-in current testing-feasibility study

2003 · W. Maly, P. Nigh · International Conference on Computer Aided Design · 222

VLSI Test Principles and Architectures

2006 · Elsevier eBooks · 212

Gentest: an automatic test-generation system for sequential circuits

1989 · W.-T. Cheng, T.J. Chakraborty · Computer · 197

A BIST scheme for an SNR test of a sigma-delta ADC

2002 · M.F. Toner, G.W. Roberts · Proceedings/Proceedings - International Test Conference · 168

Test generation costs analysis and projections

1980 · Prabhakar Goel · 167

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Testing oriented analysis of CMOS ICs with opens

2003 · W. Maly, P.K. Nag, et al. · International Conference on Computer Aided Design · 152

Circular self-test path: a low-cost BIST technique for VLSI circuits

1989 · A. Krasniewski, S. Pilarski · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 151

A BIST scheme for a SNR, gain tracking, and frequency response test of a sigma-delta ADC

1995 · M.F. Toner, G.W. Roberts · IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing · 138

System-on-Chip Test Architectures: Nanometer Design for Testability

2007 · Laung‐Terng Wang, Charles E. Stroud, et al. · 134

A case study on the implementation of the Illinois Scan Architecture

2002 · F.F. Hsu, K.M. Butler, et al. · Proceedings/Proceedings - International Test Conference · 128

An exact algorithm for selecting partial scan flip-flops

1994 · Srimat T. Chakradhar, Arun Balakrishnan, et al. · Proceedings - ACM IEEE Design Automation Conference · 123

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Laser programmable redundancy and yield improvement in a 64K DRAM

1981 · R.T. Smith, J.D. Chlipala, et al. · IEEE Journal of Solid-State Circuits · 122

VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)

2006 · Laung‐Terng Wang, Cheng‐Wen Wu, et al. · Morgan Kaufmann Publishers Inc. eBooks · 120

Reducing power consumption during test application by test vector ordering

2002 · P. Girard, C. Landrault, et al. · IEEE International Symposium on Circuits and Systems proceedings · 115

Testing VLSI with Random Access Scan

1980 · H. Ando · Medical Entomology and Zoology · 111

Works count: 2,691

Citation count: 21,680