High density embedded DRAM technology with 0.38 μm pitch in DRAM and 0.42 μm pitch in LOGIC by W/PolySi gate and Cu dual damascene metallization
Year: 2002
Type: conference-paper
Source: Symposium on VLSI Technology
Authors: N. Takenaka, M. Segawa, T. Uehara, S. Akamatsu, M. Matsumoto, K. Kurimoto, T. Ueda, H. Watanabe, T. Matsutani, K. Yoneda, A. Koshio, Y. Kato, M. Inuishi, T. Oashi, K. Tsukamoto, S. Komori, K. Tomita, T. Inbe, R. Ohsaki, T. Hanawa, S. Sakamori, M. Shirahata, J. Tsuchimoto, T. Eimori
Institutions: Panasonic (Japan), Mitsubishi Electric (Japan)
Language: English
Field: Materials Science
Domain: Physical Sciences
Open Access status: closed
OpenAlex ID: W2171386830