Year: 2002
Type: conference-paper
Abstract: This paper shows an automated flow to generate test vectors for digital IC-designs in an academic environment. The tool “Tetramax” from Synopsys has been used for Automatic Test Pattern Generation. The ATS200 hardware verification tester together with IMS software provides a structured environment for prototype analysis and for real-time comparison of the design performance against the simulated data output. Its diagnostic capabilities have been verified by hardware-based emulating stuck-at faults at various test points in a demonstrator chip and we subsequently traced back the introduced fault successfully. The used flow simplifies the generation of test vectors and subsequent debugging, especially for large digital integrated circuits.
Language: English
Subfield: Hardware and Architecture
Field: Computer Science
Domain: Physical Sciences
Open Access status: green
OpenAlex ID: W53570214