Author

C. Leyris

Observed names: C . Leyris, Cedric Leyris, CÉdric Leyris, Cédric Leyris, LEYRIS, Cédric, Leyris, Cédric

Observed institutions: Centre National de la Recherche Scientifique, Université de Montpellier, STMicroelectronics (France), Institut d'Électronique et des Systèmes, Université Montpellier 2

OpenAlex ID: A5017050908

0.13 $\mu$m SiGe BiCMOS Technology Fully Dedicated to mm-Wave Applications

2009 · GrÉgory Avenier, Malick Diop, et al. · IEEE Journal of Solid-State Circuits · 151

FDSOI devices with thin BOX and ground plane integration for 32nm node and below

2009 · C. Fenouillet-Beranger, S. Denorme, et al. · Solid-State Electronics · 147

Impact of Random Telegraph Signal in CMOS Image Sensors for Low-Light Levels

2006 · C. Leyris, F. Martinez, et al. · European Solid-State Circuits Conference (ESSCIRC) · 70

Hybrid FDSOI/bulk High-k/metal gate platform for low power (LP) multimedia technology

2009 · C. Fenouillet-Beranger, P. Perreau, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 61

Low-Frequency Noise Investigation and Noise Variability Analysis in High- $k$/Metal Gate 32-nm CMOS Transistors

2011 · Diana Lopez, S. Haendler, et al. · IEEE Transactions on Electron Devices · 57

FDSOI devices with thin BOX and ground plane integration for 32nm node and below

2008 · C. Fenouillet-Beranger, S. Denorme, et al. · European Solid-State Device Research Conference · 48

N-MOSFET oxide trap characterization induced by nitridation process using RTS noise analysis

2006 · C. Leyris, F. Martinez, et al. · Microelectronics Reliability · 37

Setting up 3D sequential integration for back-illuminated CMOS image sensors with highly miniaturized pixels with low temperature fully depleted SOI transistors

2008 · Perceval Coudrain, Perrine Batude, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 35

Oxide traps characterization of 45 nm MOS transistors by gate current R.T.S. noise measurements

2005 · F. Martinez, C. Leyris, et al. · Microelectronic Engineering · 21

Response of Correlated Double Sampling CMOS Imager Circuit to Random Telegraph Signal Noise

2006 · C. Leyris, J-c. Vildeuil, et al. · International Caribbean Conference on Devices, Circuits and Systems · 19

Investigation of a Sequential Three-Dimensional Process for Back-Illuminated CMOS Image Sensors With Miniaturized Pixels

2009 · Perceval Coudrain, Pierre Magnan, et al. · IEEE Transactions on Electron Devices · 18

Random telegraph signal noise SPICE modeling for circuit simulators

2007 · C . Leyris, S. Pilorget, et al. · European Solid-State Device Research Conference · 17

Trap competition inducing R.T.S noise in saturation range in N-MOSFETs

2005 · C. Leyris, A. Hoffmann, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 13

Mismatch Measure Improvement Using Kelvin Test Structures in Transistor Pair Configuration in Sub-Hundred Nanometer MOSFET Technology

2009 · Cecilia M. Mezzomo, Mathieu Marin, et al. · IEEE International Conference on Microelectronic Test Structures (ICMTS) · 10

Planar Bulk+ technology using TiN/Hf-based gate stack for low power applications

2008 · G. Bidal, F. Boeuf, et al. · Symposium on VLSI Technology · 9

Low-Frequency Noise Measurements as an Investigation Tool of Pixel Flickering in Cooled Hg $_0.7 hbox Cd_0.3$ Te Focal Plane Arrays

2005 · J.-P. Perez, M. Myara, et al. · IEEE Transactions on Electron Devices · 9

1/f gate tunneling current noise model of ultrathin oxide MOSFETs

2006 · F. Martinez, S. Soliveres, et al. · IEEE International Conference on Microelectronic Test Structures (ICMTS) · 5

First CMOS integration of ultra thin body and BOX (UTB2) structures on bulk direct silicon bonded (DSB) wafer with multi-surface orientations

2009 · G. Bidal, F. Boeuf, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 4

I–V and low frequency noise characterization of poly and amorphous silicon Ti- and Co-salicide resistors

2009 · J. Raoult, F. Pascal, et al. · Thin Solid Films · 4

Random telegraph signal: A sensitive and nondestructive tool for gate oxide single trap characterization

2007 · C. Leyris, F. Martinez, et al. · Microelectronics Reliability · 4

Evolution of R.T.S Source Activities in Saturation Range in N-MOSFETs for Different Oxidation Temperatures

2005 · C. Leyris · AIP conference proceedings · 4

Noise as a characterization tool for reliability under illumination of transfer gate transistor for image sensors applications

2009 · Diana Lopez, Cedric Leyris, et al. · European Solid-State Device Research Conference · 3

Study of the Low Frequency Noise of Metallic Emitter SiGeC Heterojunction Bipolar Transistors

2009 · F. Pascal, J. Raoult, et al. · AIP conference proceedings · 3

Reliability review of 250 GHz fully self aligned heterojunction bipolar transistors for millimeterwave applications

2009 · Malick Diop, Mathieu Marin, et al. · IEEE International Reliability Physics Symposium proceedings · 2

Pockets engineering impact on mismatch performance on 45nm MOSFET technologies

2009 · Cecilia M. Mezzomo, Cedric Leyris, et al. · Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon · 1

Works count: 32

Citation count: 756

H-index: 13

I10-index: 14