Get started
Author

Maud Bidaud

3DVLSI with CoolCube process: An alternative path to scaling
2015 · P. Batude, C. Fenouillet-Beranger, et al. · Symposium on VLSI Technology · 160
14nm FDSOI technology for high speed and energy efficient applications
2014 · O. Weber, E. Josse, et al. · Symposium on VLSI Technology · 107
$1.62\mu \mathrm{m}$ Global Shutter Quantum Dot Image Sensor Optimized for Near and Shortwave Infrared
2021 · J. S. Steckel, E. Josse, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 60
A conventional 45nm CMOS node low-cost platform for general purpose and low power applications
2004 · F. Boeuf, F. Arnaud, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 51
A Cost-Effective Low Power Platform for the 45-nm Technology Node
2006 · E. Josse, S. Parihar, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 37
Low cost 65nm CMOS platform for Low Power & General Purpose applications
2004 · F. Arnaud, B. Duriez, et al. · Symposium on VLSI Technology · 31
Simulation of the sub-melt laser anneal process in 45 CMOS technology—Application to the thermal pattern effects
2008 · A. Colin, P. Morin, et al. · Materials Science and Engineering B · 21
Oxide traps characterization of 45 nm MOS transistors by gate current R.T.S. noise measurements
2005 · F. Martinez, C. Leyris, et al. · Microelectronic Engineering · 21
Thin oxynitride solution for digital and mixed-signal 65nm CMOS platform
2004 · B. Tavel, M. Bidaud, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 18
High density and high speed SRAM bit-cells and ring oscillators due to laser annealing for 45nm bulk CMOS
2006 · A. Pouydebasque, B. Dumont, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 17
65nm LP/GP mix low cost platform for multi-media wireless and consumer applications
2005 · B. Tavel, B. Duriez, et al. · European Solid-State Device Research Conference · 16
Analysis of MOS Device Capacitance-Voltage Characteristics Based on the Self-Consistent Solution of the Schrödinger and Poisson Equations
1999 · C. Raynaud, J.L. Autran, et al. · MRS Proceedings · 13
High-Activation Laser Anneal Process for the 45nm CMOS Technology Platform
2007 · M. Bidaud, H. Bono, et al. · International Conference on Advanced Thermal Processing of Semiconductors · 9
New hole trapping characterization during NBTI in 65nm node technology with distinct nitridation processing
2005 · M. Denais, A. Bravaix, et al. · IEEE International Integrated Reliability Workshop final report · 9
Ge Condensation Using Rapid Thermal Oxidation for SGOI Substrate Preparation
2014 · Olivier Gourhant, Clement Pribat, et al. · ECS Transactions · 8
PDF
Gate stack optimization for 65 nm CMOS low power and high performance platform
2004 · B. Duriez, B. Tavel, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 8
Anticipation of nitrided oxides electrical thickness based on XPS measurement
2004 · J. Bienacel, D. Barge, et al. · Materials Science in Semiconductor Processing · 7
Gate Oxide Process Impact on RNCE for Advanced CMOS Transistors
2002 · F. Arnaud, M. Bidaud · European Solid-State Device Research Conference · 6
Stress-induced leakage current at low field in NMOS and PMOS devices with ultra-thin nitrided gate oxide
2004 · M Fadlallah, G Ghibaudo, et al. · Microelectronic Engineering · 5
Complete re-estimation of the gate leakage current limit for sub-0.12um technologies (EOT= 1.8-2.8nm)
2000 · M. Bidaud, F. Arnaud, et al. · European Solid-State Device Research Conference · 4
Managing annealing pattern effects in 45nm low power CMOS technology
2009 · P. Morin, F. Cacho, et al. · European Solid-State Device Research Conference · 3
Origin of local temperature variation during spike anneal and millisecond anneal
2008 · R. Beneyton, A. Colin, et al. · International Conference on Advanced Thermal Processing of Semiconductors · 3
Advanced Junction Engineering for 60nm-CMOS Transistors
2002 · M. Muller, M. Bidaud, et al. · European Solid-State Device Research Conference · 3
Triple Gate Oxide by Nitrogen Implantation Integrated in a 0.13um CMOS Flow
2002 · J.P. Carrere, A. Grouillet, et al. · European Solid-State Device Research Conference · 3
1.5–2.5 nm RTP gate oxides: process feasibility, properties and limitations
2001 · M. Bidaud, F. Guyader, et al. · Journal of Non-Crystalline Solids · 3
Works count: 34
Citation count: 635
H-index: 12
I10-index: 12
Year
Topic
Type