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K. Bala Sindhuri

Observed names: Bala Sindhuri K, Bala Sindhuri Kandula, Bala Sindhuri Kandula*, Bala Sindhuri Kandulaa, K Bala Sindhuri, K. Bala Sinduri, K.Bala Sindhuri, Kandula Bala Sindhuri, Sindhuri , K. Bala
ORCID: 0000-0001-7892-2062
Observed ORCID: 0000-0001-7892-2062
OpenAlex ID: A5067044065
Area efficient modified vedic multiplier
2016 · G. Challa Ram, Y. Rama Lakshmanna, et al. · International Conference on Circuit, Power and Computing Technologies · 69
Design and implementation of 32-bit adders using various full adders
2017 · K. Anirudh Kumar Maurya, Y. Rama Lakshmanna, et al. · Innovations in Power and Advanced Computing Technologies (i-PACT) · 36
Low power and area efficient Wallace tree multiplier using carry select adder with binary to excess-1 converter
2016 · R. Bala Sai Kesava, B. Lingeswara Rao, et al. · Conference on Advances in Signal Processing (CASP) · 33
Design of delay efficient modified 16 bit Wallace multiplier
2016 · G. Challa Ram, D. Sudha Rani, et al. · IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology · 33
Implementation and comparison of VLSI architectures of 16 bit carry select adder using Brent Kung adder
2017 · N. Udaya Kumar, K. Bala Sindhuri, et al. · Innovations in Power and Advanced Computing Technologies (i-PACT) · 24
RETRACTED ARTICLE: Artificial neural network-based secured communication strategy for vehicular ad hoc network
2022 · B. V. D. S. Sekhar, Pamula Udayaraju, et al. · Soft Computing · 18
VLSI architecture for delay efficient 32-bit multiplier using vedic mathematic sutras
2016 · G. Challa Ram, D. Sudha Rani, et al. · IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology · 17
Implementation of 64-bit Kogge Stone Carry Select Adder with ZFC for efficient area
2015 · B. Tapasvi, K. Bala Sinduri, et al. · International Conference on Electrical, Computer and Communication Technologies (ICECCT) · 16
Area Efficient VLSI Architecture for Square Root Carry Select Adder Using Zero Finding Logic
2016 · Bala Sindhuri Kandula, K. Padma Vasavi, et al. · Procedia Computer Science · 15
A Systematic Delay and Power Dominant Carry Save Adder Design
2018 · A Krishna Vamsi, N Udaya Kumar, et al. · International Conference on Smart Systems and Inventive Technology (ICSSIT) · 9
RETRACTED: Design of area efficient VLSI architecture for carry select adder using logic optimization technique
2020 · Bala Sindhuri Kandula, Padma Vasavi Kalluru, et al. · Computational Intelligence · 7
A Survey on Different Multiplier Techniques
2016 · RamaLakshmanna Y, Padma Rao G V S, et al. · International Journal of Electronics and Communication Engineering · 6
A reconfigurable graphene–VO2 based terahertz bandpass filter for differential sensing and ML-based refractive index prediction
2026 · G. Challa Ram, Asral Bahari Jambek, et al. · Physica B Condensed Matter · 5
A Comprehensive Survey of Clock-Gating Techniques for Low-Power VLSI Design
2025 · D.V.N.Bharathi, Bala Sindhuri Kandula, et al. · International Conference on Electronics, Communication and Aerospace Technology (ICECA) · 5
Graphene based THz filter design using open-loop resonator for space applications
2024 · G. Challa Ram, Naveen Kumar Maurya, et al. · Diamond and Related Materials · 5
Vanadium dioxide-based switchable and tunable dual-band THz absorber for machine learning-driven biochemical sensing
2025 · G. Challa Ram, Asral Bahari Jambek, et al. · Micro and Nanostructures · 4
FPGA design of an efficient divide-and-conquer multiplier based on multiple stage fast ripple hybrid adders for peak cancellation with IIR filters
2025 · Bala Sindhuri Kandula, Sarala Patchala, et al. · International Journal of Electronics · 4
Performance Analysis of VLSI Architecture of Dadda Multiplier Using Divide and Conquer Strategy with Approximate Adders
2024 · Bala Sindhuri Kandula, Raghumandala Devi, et al. · International Conference on Emerging Trends in Engineering and Medical Sciences (ICETEMS) · 4
Performance Evaluation of Vedic Multiplier Using Multiplexer-Based Adders
2018 · N. Udaya Kumar, K. Bala Sindhuri, et al. · Lecture notes in electrical engineering · 4
Implementation of Vedic Multiplier Using Modified Architecture by Routing Rearrangement for High-Optimization
2018 · G Sai Chandra Teja, K Bala Sindhuri, et al. · International Conference on Communication and Electronics Systems (ICCES) · 4
Implementation of 64 Bit KoggeStone Carry Select Adder with BEC for Efficient Area
2015 · B. Tapasvi, K. Bala Sinduri, et al. · 4
VLSI Architecture of Efficient Hybrid Multiplier Using Hybrid Adder
2023 · Bala Sindhuri Kandula, Manikanta J.S.S.D, et al. · International Journal of Electrical and Electronics Engineering · 3
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Design of Area and Power Potent Booth Multiplier Using Multiplexer
2018 · V Soma Sandeep, K Bala Sindhuri, et al. · International Conference on Communication and Electronics Systems (ICCES) · 3
Implementation of 32-Bit Carry Select Adder using Brent-Kung Adder
2016 · P. Nithin, N. Udaya Kumar, et al. · Indian Journal of Science and Technology · 3
Real-Time IoT-based Vehicle Accident Detection and Emergency Response System using Multi-Sensor Fusion
2025 · A M S V Sushma, A Aswini Priyanka, et al. · International Conference on Intelligent Communication Technologies and Virtual Mobile Networks (ICICV) · 2
Works count: 63
Citation count: 351
H-index: 9
I10-index: 9
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