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L. Nebrich
Observed names:
L Nebrich,
Lars Nebrich,
Nebrich, L.,
Nebrich, Lars
Institution:
Fraunhofer Research Institution for Microsystems and Solid State Technologies
Observed institutions:
Christian-Albrechts-Universität zu Kiel,
Fraunhofer Research Institution for Microsystems and Solid State Technologies,
Fraunhofer Institute for Reliability and Microintegration,
Fraunhofer-Gesellschaft
ORCID:
0009-0009-4350-5619
Observed ORCID:
0009-0009-4350-5619
OpenAlex ID:
A5081497113
3D Integration of CMOS transistors with ICV-SLID technology
2005
·
Robert Wieland
, Detlef Bonfert
, et al.
·
Microelectronic Engineering
·
38
3D integration of image sensor SiP using TSV silicon interposer
2009
·
M. Juergen Wolf
, K. Zoschke
, et al.
·
IEEE Electronics Packaging Technology Conference (EPTC)
·
24
3D image sensor SiP with TSV silicon interposer
2009
·
I. Limansyah
, M. J. Wolf
, et al.
·
IEEE Electronic Components and Technology Conference (ECTC)
·
22
3D-Integrated Superconducting qubits: CMOS-Compatible, Wafer-Scale Processing for Flip-Chip Architectures
2025
·
Mayer, T.
, Bender, H.
, et al.
·
arXiv (Cornell University)
·
7
PDF
On the initial temporal current characteristics of thin oxide devices depending on constant voltage pulse sequences
2000
·
J.-W Zahlmann-Nowitzki
, L Nebrich
, et al.
·
Microelectronics Reliability
·
4
Wafer-Scale Electrical Characterization of Al/AlxOy/Al Tunnel Junctions for Process Monitoring at Room Temperature
2026
·
Simon Johann Klaus Lang
, Ignaz Eisele
, et al.
·
Nanomaterials
·
3
PDF
3D Process Integration – Requirements and Challenges
2008
·
Juergen Max Wolf
, Armin Klumpp
, et al.
·
MRS Proceedings
·
3
A Demonstration of Multifloating Superconducting Qubits on a 3-D Flip-Chip Platform With TLS Loss Mitigation via Apertures
2025
·
Zhen Luo
, Thomas Mayer
, et al.
·
IEEE Microwave and Wireless Technology Letters
·
2
Silicon-interposer with high density Cu-filled TSVs
2010
·
R. Wieland
, K. Zoschke
, et al.
·
IEEE International D Systems Integration Conference
·
2
High quality strained Si/SiGe substrates for CMOS and optical devices
2005
·
J. Weber
, L. Nebrich
, et al.
·
Microelectronic Engineering
·
2
Stability studies on subtractively-fabricated CMOS-compatible superconducting transmon qubits
2025
·
Dhieb, Chawki
, Weber, Johannes
, et al.
·
arXiv (Cornell University)
·
1
PDF
Experimental study of the current characteristics of thin silicon oxide films under dynamic stress
2001
·
J.-W Zahlmann-Nowitzki
, L Nebrich
, et al.
·
Solid-State Electronics
·
1
On the influence of the variation of measurement conditions on the FNT characteristics of stressed thin silicon oxides
2001
·
J.-W Zahlmann-Nowitzki
, L Nebrich
, et al.
·
Microelectronics Reliability
·
1
Wafer-Scale Electrical Characterization of Al/AlxOy/Al Tunnel Junctions for Process Monitoring at Room Temperature
2026
·
Lang, Simon
, Eisele, Ignaz
, et al.
·
Fraunhofer-Publica (Fraunhofer-Gesellschaft)
Process integration of infrared-sensitive PIN photodiodes and CMOS transistors in a single-SiGe substrate
2004
·
L. Nebrich
, K. Neumeier
, et al.
·
Materials Science in Semiconductor Processing
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Works count:
29
Citation count:
110
H-index:
4
I10-index:
3
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