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B. Tavel

Observed names: B Tavel, Brice Tavel, Tavel, Brice
OpenAlex ID: A5066992015
75 nm damascene metal gate and high-k integration for advanced CMOS devices
2003 · B. Guillaumot, X. Garros, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 72
Innovative Smart Cut™ Piezo On Insulator (POI) Substrates for 5G acoustic filters
2020 · E. Butaud, S. Ballandras, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 69
Smart Cut™ Piezo On Insulator (POI) substrates for high performances SAW components
2020 · Eric Butaud, Brice Tavel, et al. · IEEE International Ultrasonics Symposium · 64
Totally silicided (CoSi/sub 2/) polysilicon: a novel approach to very low-resistive gate (∼2Ω/□) without metal CMP nor etching
2002 · B. Tavel, T. Skotnicki, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 57
16 nm planar NMOSFET manufacturable within state-of-the-art CMOS process thanks to specific design and optimisation
2002 · F. Boeuf, T. Skotnicki, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 56
A conventional 45nm CMOS node low-cost platform for general purpose and low power applications
2004 · F. Boeuf, F. Arnaud, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 51
Low cost 65nm CMOS platform for Low Power & General Purpose applications
2004 · F. Arnaud, B. Duriez, et al. · Symposium on VLSI Technology · 31
SON (Silicon-On-Nothing) P-MOSFETs with totally silicided (CoSi/sub 2/) polysilicon on 5 nm-thick Si-films: the simplest way to integration of metal gates on thin FD channels
2003 · S. Monfray, T. Skotnicki, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 25
Oxide traps characterization of 45 nm MOS transistors by gate current R.T.S. noise measurements
2005 · F. Martinez, C. Leyris, et al. · Microelectronic Engineering · 21
Thin oxynitride solution for digital and mixed-signal 65nm CMOS platform
2004 · B. Tavel, M. Bidaud, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 18
0.248μm/sup 2/ and 0.334μm/sup 2/ conventional bulk 6T-SRAM bit -cells for 45nm node low cost - general purpose applications
2005 · F. Boeuf, F. Arnaud, et al. · Symposium on VLSI Technology · 16
65nm LP/GP mix low cost platform for multi-media wireless and consumer applications
2005 · B. Tavel, B. Duriez, et al. · European Solid-State Device Research Conference · 16
Poly-gate replacement through contact hole (PRETCH): a new method for high-K/metal gate and multi-oxide implementation on chip
2005 · S. Harrison, P. Coronel, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 15
A Single Smart Cut POI Substrate Design for UHF, L and S Band Filters
2021 · E. Butaud, T. Laroche, et al. · European Microwave Conference (EuMC) · 12
Ultra-low cost and high performance 65nm CMOS device fabricated with plasma doping
2004 · F. Lallement, B. Duriez, et al. · Symposium on VLSI Technology · 11
65 nm Device Manufacture Using Shaped E-Beam Lithography
2004 · Laurent Pain, Murielle Jurdit, et al. · Japanese Journal of Applied Physics · 10
New hole trapping characterization during NBTI in 65nm node technology with distinct nitridation processing
2005 · M. Denais, A. Bravaix, et al. · IEEE International Integrated Reliability Workshop final report · 9
MOSFET matching improvement in 65nm technology providing gain on both analog and SRAM performances
2005 · R. Difrenza, K. Rochereau, et al. · IEEE International Conference on Microelectronic Test Structures (ICMTS) · 8
Gate stack optimization for 65 nm CMOS low power and high performance platform
2004 · B. Duriez, B. Tavel, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 8
High performance 40 nm nMOSFETs with HfO/sub 2/ gate dielectric and polysilicon damascene gate
2003 · B. Tavel, X. Garros, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 7
Gate Oxide Cleans on Single Wafer Tool
2007 · Philippe Garnier, Tony Vessa, et al. · ECS Transactions · 6
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Towards a better EOT - mobility trade-off in high-k oxide/metal gate CMOS devices
2004 · M. Muller, S. Duguay, et al. · IEEE Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS) · 6
Manufacturing concerns for advanced CMOS circuit realization EBDW alternative solution for cost and cycle time reductions
2004 · Laurent Pain, M. Jurdit, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 4
New generation of composite substrates based on a layer of LiTaO3 on silicon for surface acoustic waves components
2020 · Clairet, Alexandre, Courjon, Emilie, et al. · HAL · 3
65nm LP/GP mix low cost platform for multi-media wireless and consumer applications
2006 · B. Tavel, B. Duriez, et al. · Solid-State Electronics · 2
Works count: 34
Citation count: 606
H-index: 13
I10-index: 16
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