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Rabah Kies

Temperature dependence of the Fowler–Nordheim current in metal-oxide-degenerate semiconductor structures
1995 · G. Pananakakis, G. Ghibaudo, et al. · Journal of Applied Physics · 133
7-Levels-Stacked Nanosheet GAA Transistors for High Performance Computing
2020 · S. Barraud, B. Previtali, et al. · Symposium on VLSI Technology · 122
Low leakage and low variability Ultra-Thin Body and Buried Oxide (UT2B) SOI technology for 20nm low power CMOS and beyond
2010 · F. Andrieu, O. Weber, et al. · Symposium on VLSI Technology · 109
Lowering the Reset Current and Power Consumption of Phase-Change Memories with Carbon-Doped Ge2Sb2Te5
2012 · Q. Hubert, C. Jahan, et al. · IEEE International Memory Workshop (IMW) · 42
Novel integration process and performances analysis of Low STandby Power (LSTP) 3D multi-channel CMOSFET (MCFET) on SOI with metal / high-K gate stack
2008 · E. Bernard, T. Ernst, et al. · Symposium on VLSI Technology · 35
28nm FDSOI CMOS Technology (FEOL and BEOL) Thermal Stability for 3D Sequential Integration: Yield and Reliability Analysis
2020 · C. Cavalcante, C. Fenouillet-Beranger, et al. · Symposium on VLSI Technology · 33
New insight on the charge trapping mechanisms of SiN-based memory by atomistic simulations and electrical modeling
2009 · E. Vianello, L. Perniola, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 28
Generalized trapping kinetic model for the oxide degradation after Fowler–Nordheim uniform gate stress
1997 · G. Pananakakis, G. Ghibaudo, et al. · Journal of Applied Physics · 24
Reliability of ultra-thin buried oxides for multi-VT FDSOI technology
2014 · G. Besnard, X. Garros, et al. · Solid-State Electronics · 23
All-Operation-Regime Characterization and Modeling of Drain Current Variability in Junctionless and Inversion-Mode FDSOI Transistors
2020 · D. Bosch, J. P. Colinge, et al. · Symposium on VLSI Technology · 22
Reversibility of charge trapping and SILC creation in thin oxides after stress/anneal cycling
1998 · P. Riess, R. Kies, et al. · Microelectronics Reliability · 19
Scalability of split-gate charge trap memories down to 20nm for low-power embedded memories
2011 · L. Masoero, G. Molas, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 18
First Demonstration of Low Temperature (≤500°C) CMOS Devices Featuring Functional RO and SRAM Bitcells toward 3D VLSI Integration
2020 · C. Fenouillet-Beranger, L. Brunet, et al. · Symposium on VLSI Technology · 16
Accelerated dielectric breakdown and wear out standard testing methods and structures for reliability evaluation of thin oxides
1999 · G Ghibaudo, G Pananakakis, et al. · Microelectronics Reliability · 15
Performance and Modeling of Si-Nanocrystal Double-Layer Memory Devices With High- $k$ Control Dielectrics
2012 · G. Gay, G. Molas, et al. · IEEE Transactions on Electron Devices · 14
A method for the assessment of oxide charge density and centroid in metal-oxide-semiconductor structures after uniform gate stress
1996 · R. Kies, T. Egilsson, et al. · Applied Physics Letters · 12
Improvements in low temperature (<625°C) FDSOI devices down to 30nm gate length
2012 · C. Xu, P. Batude, et al. · International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) · 10
FDSOI devices: A solution to achieve low junction leakage with low temperature processes (≤ 650°C)
2012 · B. Sklenard, C. Xu, et al. · Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon · 9
Investigation of the role of H-related defects in Al2O3 blocking layer on charge-trap memory retention by atomistic simulations and device physical modelling
2010 · G. Molas, L. Masoero, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 9
New physical model for ultra-scaled 3D nitride-trapping non-volatile memories
2008 · E. Nowak, M. Bocquet, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 9
Highly automated sequence for Phase Change Memory test structure characterization
2010 · A Toffoli, A Fantini, et al. · IEEE International Conference on Microelectronic Test Structures (ICMTS) · 8
Temperature Dependence of Fowler-Nordheim Emission Tunneling Current in MOS Structures
1994 · R. Kies, C. Papadas, et al. · European Solid-State Device Research Conference · 8
Dense N over CMOS 6T SRAM cells using 3D Sequential Integration
2017 · C.-M V. Lu, C. Fenouillet-Beranger, et al. · International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) · 6
Hybrid silicon nanocrystals/SiN charge trapping layer with high-k dielectrics for FN and CHE programming
2010 · G. Gay, G. Molas, et al. · International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) · 6
Investigation of charge-trap memories with AlN based band engineered storage layers
2011 · G. Molas, J.P. Colonna, et al. · Solid-State Electronics · 5
Works count: 45
Citation count: 770
H-index: 14
I10-index: 17
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