Get started
Author

Michael E. Orshansky

Observed names: M Orshansky, M. Orshansky, Michael Orshansky, Orshansky, Michael, Orshansky, Michael E.
ORCID: 0000-0002-6223-4748
Observed ORCID: 0000-0002-6223-4748
OpenAlex ID: A5090899796
Approximate computing: An emerging paradigm for energy-efficient design
2013 · Jie Han, Michael Orshansky · IEEE European Test Symposium (ETS) · 1,113
New paradigm of predictive MOSFET and interconnect modeling for early circuit simulation
2002 · Y. Cao, T. Sato, et al. · Custom Integrated Circuits Conference · 507
Design for Manufacturability and Statistical Design
2007 · Michael Orshansky, Sani R. Nassif, et al. · Springer eBooks · 214
A general probabilistic framework for worst case timing analysis
2002 · Michael Orshansky, Kurt Keutzer · ACM/IEEE Design Automation Conference (DAC) · 195
BulletProof: A Defect~Tolerant CMP Switch Architecture
2006 · K. Constantinides, S. Plaza, et al. · IEEE International Symposium on High-Performance Computer Architecture (HPCA) · 192
FASER: Fast Analysis of Soft Error Susceptibility for Cell-Based Designs
2006 · Bin Zhang, Wei-Shen Wang, et al. · International Symposium on Quality Electronic Design (ISQED) · 177
Minimization of dynamic and static power through joint assignment of threshold voltages and sizing optimization
2003 · D. Nguyen, A. Davare, et al. · International Symposium on Low Power Electronics and Design (ISLPED) · 151
Impact of spatial intrachip gate length variability on the performance of high-speed digital circuits
2002 · M. Orshansky, L. Milor, et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 146
An efficient algorithm for statistical minimization of total power under timing yield constraints
2005 · Murari Mani, Anirudh Devgan, et al. · ACM/IEEE Design Automation Conference (DAC) · 130
Modeling and synthesis of quality-energy optimal approximate adders
2012 · Jin Miao, Ku He, et al. · 122
Fast statistical timing analysis handling arbitrary delay correlations
2004 · Michael Orshansky, Arnab Bandyopadhyay · ACM/IEEE Design Automation Conference (DAC) · 114
A general probabilistic framework for worst case timing analysis
2002 · M. Orshansky, K. Keutzer · ACM/IEEE Design Automation Conference (DAC) · 105
Characterization of Spatial Intrafield Gate CD Variability, Its Impact on Circuit Performance, and Spatial Mask-Level Correction
2004 · M. Orshansky, L. Milor, et al. · IEEE Transactions on Semiconductor Manufacturing · 99
Impact of systematic spatial intra-chip gate length variability on performance of high-speed digital circuits
2015 · Michael Orshansky, Linda Milor, et al. · 71
Approximate logic synthesis under general error magnitude and frequency constraints
2013 · Jin Miao, Andreas Gerstlauer, et al. · International Conference on Computer Aided Design · 69
Analytical modeling of SRAM dynamic stability
2006 · Bin Zhang, Ari Arapostathis, et al. · Digest of technical papers/Digest of technical papers - IEEE/ACM International Conference on Computer-Aided Design · 69
A new statistical optimization algorithm for gate sizing
2004 · M. Mani, M. Orshansky · IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD) · 69
NBTI-aware DVFS
2010 · Mehmet Basoglu, Michael Orshansky, et al. · International Symposium on Low Power Electronics and Design (ISLPED) · 66
Joint design-time and post-silicon minimization of parametric yield loss using adjustable robust optimization
2006 · Murari Mani, Ashish K. Sing, et al. · Digest of technical papers/Digest of technical papers - IEEE/ACM International Conference on Computer-Aided Design · 65
A Strong Subthreshold Current Array PUF Resilient to Machine Learning Attacks
2019 · Haoyu Zhuang, Xiaodan Xi, et al. · IEEE Transactions on Circuits and Systems I Regular Papers · 64
Analytical Modeling of SRAM Dynamic Stability
2006 · Bin Zhang, Ari Arapostathis, et al. · Digest of technical papers/Digest of technical papers - IEEE/ACM International Conference on Computer-Aided Design · 62
Enabling Efficient Analog Synthesis by Coupling Sparse Regression and Polynomial Optimization
2014 · Ye Wang, Michael Orshansky, et al. · ACM/IEEE Design Automation Conference (DAC) · 60
Approximate logic synthesis under general error magnitude and frequency constraints
2013 · Miao Jin, Andreas Gerstlauer, et al. · 60
A sequence dependent challenge-response PUF using 28nm SRAM 6T bit cell
2017 · Supreet Jeloka, Kaiyuan Yang, et al. · Symposium on VLSI Circuits · 59
Strong subthreshold current array PUF with 265 challenge-response pairs resilient to machine learning attacks in 130nm CMOS
2017 · Xiaodan Xi, Haoyu Zhuang, et al. · Symposium on VLSI Circuits · 59
Works count: 180
Citation count: 5,534
H-index: 37
I10-index: 75
Year
Topic
Type