Author

T. Takeuchi

Observed name: Takayuki Takeuchi Takayuki Takeuchi

Institution: NEC (Japan)

Observed institutions: NEC (Japan), Panasonic (Japan)

OpenAlex ID: A5113780539

Preparation and Properties of (Pb, La)TiO3 Pyroelectric Thin Films by RF-Magnetron Sputtering

1993 · Nobuaki Nagao, Takayuki Takeuchi Takayuki Takeuchi, et al. · Japanese Journal of Applied Physics · 45

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A 60-ns 1-Mb nonvolatile ferroelectric memory with a nondriven cell plate line write/read scheme

1996 · H. Koike, T. Otsuki, et al. · IEEE Journal of Solid-State Circuits · 42

A call admission control for ATM networks based on individual multiplexed traffic characteristics

2002 · T. Murase, H. Suzuki, et al. · International Conference on Communications · 38

A 60 ns 1 Mb nonvolatile ferroelectric memory with non-driven cell plate line write/read scheme

2002 · H. Koike, T. Otsuki, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 24

A burst traffic control strategy for ATM networks

2002 · H. Suzuki, T. Murase, et al. · Globecom · 24

Comprehensive Chemistry Designs in Porous SiOCH Film Stacks and Plasma Etching Gases for Damageless Cu Interconnects in Advanced ULSI Devices

2008 · Y. Hayashi, H. Ohtake, et al. · IEEE Transactions on Semiconductor Manufacturing · 21

Compositional design of Pb(Zr, Ti)O/sub 3/ for highly reliable ferroelectric memories

2002 · N. Inoue, T. Takeuchi, et al. · IEEE Transactions on Electron Devices · 16

A ferroelectric capacitor over bit-line (F-COB) cell for high density nonvolatile ferroelectric memories

2002 · N. Tanabe, T. Matsuki, et al. · Symposium on VLSI Technology · 14

Robust porous SiOCH/Cu interconnects with ultrathin sidewall protection liners

2006 · M. Tada, T. Tamura, et al. · IEEE Transactions on Electron Devices · 13

Highly reliable, 65 nm-node Cu dual damascene interconnects with full porous-SiOCH (k=2.5) films for low-power ASICs

2004 · M. Ueki, M. Narihiro, et al. · Symposium on VLSI Technology · 11

A 65nm-node, Cu interconnect technology using porous SiOCH film (k=2.5) covered with ultra-thin, low-k pore seal (k=2.7)

2004 · M. Tada, Y. Harada, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 9

Cu dual damascene interconnects in porous organosilica film with organic hard-mask and etch-stop layers for 70 nm-node ULSIs

2003 · M. Tada, Y. Harada, et al. · IEEE International Interconnect Technology Conference (IITC) · 9

High tolerance operation of 1T/2C FeRAMs for the variation of cell capacitors characteristics

2002 · N. Tanabe, S. Kobayashi, et al. · Symposium on VLSI Technology · 9

45nm-node Interconnects with Porous SiOCH-Stacks, Tolerant of Low-Cost Packaging Applications

2007 · N. Inoue, M. Tagami, et al. · IEEE International Interconnect Technology Conference (IITC) · 8

High-Performance Cu-Interconnects with Novel Seamless Low-k SiOCH Stacks (SEALS) Featured by Compositional Modulation Process for 45nm-Node ULSI Devices

2006 · M. Tagami, H. Ohtake, et al. · Symposium on VLSI Technology · 7

A metallurgical prescription for electromigration (EM) reliability improvment in scaled-down, Cu dual damascene interconnects

2006 · M. Tada, M. Abe, et al. · IEEE International Interconnect Technology Conference (IITC) · 6

Plasma Co-polymerization Technology with Molecular-level Structure Tightening in "In-situ" SiOCH Stacks for 32nm-node Cu Interconnects

2006 · M. Tada, H. Yamamoto, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 6

Feasibility study of a novel molecular-pore-stacking (MPS), SiOCH film in fully-scale-down, 45nm-node Cu damascene interconnects

2005 · M. Tada, H. Ohtake, et al. · Symposium on VLSI Technology · 6

Novel molecular-structure design for PECVD porous SiOCH films toward 45nm node, ASICs with k=2.3

2004 · Y. Hayashi, F. Itoh, et al. · IEEE International Interconnect Technology Conference (IITC) · 6

High performance Cu interconnects with damage-less full molecular-pore-stack (MPS) SiOCH for 32nm-node LSIs and beyond

2008 · M. Ueki, M. Tagami, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 4

Cost-effective and High Performance Cu Interconnects (keff=2.75) with Continuous SiOCH Stack Incorporating a Low-k Barrier Cap (k=3.1)

2007 · M. Ueki, H. Yamamoto, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 4

A robust 45 nm-node, dual damascene interconnects with high quality cu/barrier interface by a novel oxygen absorption process

2005 · M. Abe, K. Motoyama, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 3

Preparation and properties of lanthanum modified PbTiO/sub 3/ thin films by rf-magnetron sputtering

2002 · K. Iijima, T. Takeuchi, et al. · IEEE International Symposium on Applications of Ferroelectrics (ISAF) · 3

Sputtering process design of PZT capacitors for stable FeRAM operation

2002 · N. Inoue, T. Takeuchi, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 3

RF performance upgrading of low-power 40nm-node CMOS devices by extremely low-resistance partially-thickened local (PTL)-interconnects

2009 · K. Hijioka, J. Kawahara, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 2

Works count: 30

Citation count: 336

H-index: 10

I10-index: 10