Author

Shih‐Lien Lu

Observed names: Lu, Lu, Shih-Lien, Shih-Lien L Lu, Shih-Lien L. Lu, Shih-Lien Linus Lu, Shih-Lien Lu, Shih-lien Lu, Shih‐Lien L. Lu

Observed institutions: Oregon State University, Taiwan Semiconductor Manufacturing Company (United States), Intel (United States), Taiwan Semiconductor Manufacturing Company (Taiwan), Intel (Taiwan), Intel (Malaysia), Intel (India)

OpenAlex ID: A5113824454

Energy-Efficient and Metastability-Immune Resilient Circuits for Dynamic Variation Tolerance

2009 · Keith A. Bowman, James W. Tschanz, et al. · IEEE Journal of Solid-State Circuits · 351

A 45 nm Resilient Microprocessor Core for Dynamic Variation Tolerance

2010 · Keith A. Bowman, James W. Tschanz, et al. · IEEE Journal of Solid-State Circuits · 265

Trading off Cache Capacity for Reliability to Enable Low Voltage Operation

2008 · Chris Wilkerson, Hongliang Gao, et al. · Proceedings - International Symposium on Computer Architecture/Proceedings · 248

Speeding up processing with approximation circuits

2004 · Shih-Lien Lu · Computer · 228

Reducing cache power with low-cost, multi-bit error-correcting codes

2010 · Chris Wilkerson, Alaa R. Alameldeen, et al. · Proceedings - International Symposium on Computer Architecture/Proceedings · 196

Technology comparison for large last-level caches (L3Cs): Low-leakage SRAM, low write-energy STT-RAM, and refresh-optimized eDRAM

2013 · Mu-Tien Chang, P. Rosenfeld, et al. · IEEE International Symposium on High-Performance Computer Architecture (HPCA) · 174

RAMP: Research Accelerator for Multiple Processors

2007 · John Wawrzynek, David Patterson, et al. · IEEE Micro · 171

DRAM Refresh Mechanisms, Penalties, and Trade-Offs

2015 · Ishwar Bhati, Mu-Tien Chang, et al. · IEEE Transactions on Computers · 165

Improving cache lifetime reliability at ultra-low voltages

2009 · Zeshan Chishti, Alaa R. Alameldeen, et al. · IEEE/ACM International Symposium on Microarchitecture (MICRO) · 165

Energy-efficient cache design using variable-strength error-correcting codes

2011 · Alaa R. Alameldeen, Ilya Wagner, et al. · Proceedings - International Symposium on Computer Architecture/Proceedings · 152

Coming challenges in microarchitecture and architecture

2001 · R. Ronen, A. Mendelson, et al. · Proceedings of the IEEE · 141

Circuit techniques for dynamic variation tolerance

2009 · Keith Bowman, James Tschanz, et al. · ACM/IEEE Design Automation Conference (DAC) · 128

Sandbox Prefetching: Safe run-time evaluation of aggressive prefetchers

2014 · Seth H Pugsley, Zeshan Chishti, et al. · IEEE International Symposium on High-Performance Computer Architecture (HPCA) · 126

Flexible auto-refresh

2015 · Ishwar Bhati, Zeshan Chishti, et al. · Proceedings - International Symposium on Computer Architecture/Proceedings · 95

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2 GHz 2 Mb 2T Gain Cell Memory Macro With 128 GBytes/sec Bandwidth in a 65 nm Logic Process Technology

2009 · Dinesh Somasekhar, Yibin Ye, et al. · IEEE Journal of Solid-State Circuits · 94

Energy-Efficient and Metastability-Immune Timing-Error Detection and Instruction-Replay-Based Recovery Circuits for Dynamic-Variation Tolerance

2008 · Keith A. Bowman, James W. Tschanz, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 85

Bloom filtering cache misses for accurate data speculation and prefetching

2014 · Jih-Kwon Peir, Shih-Chang Lai, et al. · International Conference on Supercomputing · 76

Novel FPGA based Haar classifier face detection algorithm acceleration

2008 · Changjian Gao, Shih-Lien Lu · International Conference on Field Programmable Logic and Applications (FPL) · 70

Performance improvement with circuit-level speculation

2000 · Tong Liu, Shih-Lien Lu · IEEE/ACM International Symposium on Microarchitecture (MICRO) · 66

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Improving DRAM latency with dynamic asymmetric subarray

2015 · Shih-Lien Lu, Ying-Chen Lin, et al. · IEEE/ACM International Symposium on Microarchitecture (MICRO) · 65

A 45nm resilient and adaptive microprocessor core for dynamic variation tolerance

2010 · James Tschanz, Keith Bowman, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 65

PVT-and-aging adaptive wordline boosting for 8T SRAM power reduction

2010 · Arijit Raychowdhury, Bibiche Geuskens, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 63

Reducing cache power with low-cost, multi-bit error-correcting codes

2010 · Chris Wilkerson, Alaa R. Alameldeen, et al. · ACM SIGARCH Computer Architecture News · 54

Adaptive Cache Design to Enable Reliable Low-Voltage Operation

2010 · Alaa R. Alameldeen, Zeshan Chishti, et al. · IEEE Transactions on Computers · 48

Research accelerator for multiple processors

2006 · David Patterson, Arvind, et al. · IEEE Hot Chips Symposium · 48

Works count: 139

Citation count: 4,214

H-index: 32

I10-index: 54