Performance and reliability of sub-100nm TaSiN metal gate fully-depleted SOI devices with high-k (HfO/sub 2/) gate dielectric
Year: 2004
Type: conference-paper
Source: Symposium on VLSI Technology
Authors: A.V.-Y. Thean, A. Vandooren, S. Kalpat, Y. Du, I. To, J. Hughes, T. Stephens, B. Goolsby, T. White, A. Barr, L. Mathew, M. Huang, S. Egley, M. Zavala, D. Eades, K. Sphabmixay, J. Schaeffer, D. Triyoso, M. Rossow, D. Roan, D. Pham, R. Rai, S. Murphy, B.-Y. Nguyen, B.E. White, A. Duvallet, T. Dao, J. Mogab
Institutions: Motorola (United States), STMicroelectronics (United States)
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: closed
OpenAlex ID: W2017215403