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M. Sakao

Observed name: M Sakao
OpenAlex ID: A5022201765
A 30-ns 64-Mb DRAM with built-in self-test and self-repair function
1992 · A. Tanabe, T. Takeshima, et al. · IEEE Journal of Solid-State Circuits · 81
A capacitor-over-bit-line (COB) cell with a hemispherical-grain storage node for 64 Mb DRAMs
2002 · M. Sakao, N. Kasai, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 42
A high-density data-path generator with stretchable cells
1994 · Y. Tsujihashi, H. Matsumoto, et al. · IEEE Journal of Solid-State Circuits · 14
A 250-Mb/s/pin, 1-Gb double-data-rate SDRAM with a bidirectional delay and an interbank shared redundancy scheme
2000 · Y. Takai, M. Fujita, et al. · IEEE Journal of Solid-State Circuits · 12
A 30 ns 64 Mb DRAM with built-in self-test and repair function
2003 · H. Koike, A. Tanabe, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 10
Device Technology for embedded DRAM utilizing stacked MIM(Metal-Insulator-Metal) Capacitor
2006 · Y. Yamagata, H. Shirai, et al. · Custom Integrated Circuits Conference · 6
A 250 Mb/s 1 Gb double data rate SDRAM with a bi-directional delay and an inter-bank shared redundancy scheme
2003 · Y. Takai, M. Fujita, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 6
A new DRAM cell with a transistor on a lateral epitaxial silicon layer (TOLE cell)
1990 · K. Terada, T. Ishijima, et al. · IEEE Transactions on Electron Devices · 6
A new soft-error immune DRAM cell with a transistor on a lateral epitaxial silicon layer (TOLE cell)
1987 · T. Kubota, T. Ishijima, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 6
Low-temperature integrated process below 500°C for thin Ta/sub 2/O/sub 5/ capacitor for giga-bit DRAMs
2002 · Y. Takaishi, M. Sakao, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 4
Ultra-high-performance 0.13-μm embedded DRAM technology using TiN/HfO/sub 2//TiN/W capacitor and body-slightly-tied SOI
2003 · Y. Aoki, T. Ueda, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 3
A 0.15 μm logic based embedded DRAM technology featuring 0.425 μm/sup 2/ stacked cell using MIM (metal-insulator-metal) capacitor
2002 · M. Takeuchi, K. Inoue, et al. · Symposium on VLSI Technology · 3
A high-performance 0.18-μm merged DRAM/Logic technology featuring 0.45-μm/sup 2/ stacked capacitor cell
2003 · M. Hamada, K. Inoue, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 2
A New CMOS Structure Using a Transistor on a Lateral Epitaxial Silicon Layer
1988 · T. Ishijima, K. Terada, et al. · International Conference on Solid State Devices and Materials (SSDM) · 2
Overview and Future Challenges eDRAM Technologies
2007 · H. sugimura, T. Wake, et al. · International Conference on Solid State Devices and Materials (SSDM) · 1
A CMOS/partial-SOI structure for future ULSIs
2003 · K. Terada, T. Ishijima, et al. · IEEE SOS/SOI Technology Conference · 1
A Capacitor over Bit-Line (COB) Stacked Capacitor Cell Using Local Interconnect Layer for 64 MbDRAMs
1993 · N. Kasai, M. Sakao, et al. · IEICE Transactions on Electronics · 1
A 1.71-million transistor CMOS CPU chip with a testable cache architecture
1993 · Y. Saito, Y. Shimazu, et al. · IEEE Journal of Solid-State Circuits · 1
Embedded DRAM Technology for Consumer Electronics
2008 · H. Shirai, Ryousuke Ishikawa, et al. · IEICE Technical Report; IEICE Tech. Rep.
Device Technology for embedded DRAM utilizing stacked MIM(Metal-Insulator-Metal) Capacitor
2007 · Tanigawa Takaho, Yasushi Yamagata, et al. · IEICE Technical Report; IEICE Tech. Rep.
A 0.13 μm full metal embedded DRAM technology targeting on 1.2 V, 450 MHz operation
2002 · S. Arai, T. Sakoh, et al. · Technical digest - International Electron Devices Meeting/Technical digest
Logic based Embedded DRAM technologies targeting Low Voltage and High Speed Operation
2002 · Susumu Arai, T. Sakoh, et al. · 半導体・集積回路技術シンポジウム講演論文集
A VLSI chip set for a large-scale parallel inference machine: PIM/m
1993 · H. Machida, H. Ando, et al. · IEEE Journal of Solid-State Circuits
64Mb・DRAM用の半球状の結晶粒記憶節点を持つビットライン上のコンデンサ(COB)セル
1990 · M Sakao, N Kasai, et al. · Technical digest - International Electron Devices Meeting/Technical digest
Works count: 24
Citation count: 201
H-index: 6
I10-index: 5
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