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Claude Ortolland

Benchmarking SOI and bulk FinFET alternatives for PLANAR CMOS scaling succession
2010 · T. Chiarella, L. Witters, et al. · Solid-State Electronics · 129
22nm High-performance SOI technology featuring dual-embedded stressors, Epi-Plate High-K deep-trench embedded DRAM and self-aligned Via 15LM BEOL
2012 · S. Narasimha, P. Chang, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 95
Method for Managing the Stress Due to the Strained Nitride Capping Layer in MOS Transistors
2007 · Stphane Orain, Vincent Fiori, et al. · IEEE Transactions on Electron Devices · 43
Stress Memorization Technique (SMT) Optimization for 45nm CMOS
2006 · C. Ortolland, P. Morin, et al. · Symposium on VLSI Technology · 42
Stress Memorization Technique—Fundamental Understanding and Low-Cost Integration for Advanced CMOS Technology Using a Nonselective Process
2009 · Claude Ortolland, Yasutoshi Okuno, et al. · IEEE Transactions on Electron Devices · 35
Silicide yield improvement with NiPtSi formation by laser anneal for advanced low power platform CMOS technology
2009 · C. Ortolland, E. Rosseel, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 31
Migrating from planar to FinFET for further CMOS scaling: SOI or bulk?
2009 · T. Chiarella, L. Witters, et al. · European Solid-State Circuits Conference (ESSCIRC) · 29
Nonuniform Mobility-Enhancement Techniques and Their Impact on Device Performance
2008 · Fabrice Payet, Frederic Boeuf, et al. · IEEE Transactions on Electron Devices · 23
Electrical characterization and mechanical modeling of process induced strain in 65 nm CMOS technology
2004 · C. Ortolland, S. Orain, et al. · European Solid-State Circuits Conference (ESSCIRC) · 18
Process technology for IBM 14-nm processor designs featuring silicon-on-insulator FinFETs
2018 · S. R. Stiffler, R. Ramachandran, et al. · IBM Journal of Research and Development · 17
0.248μm/sup 2/ and 0.334μm/sup 2/ conventional bulk 6T-SRAM bit -cells for 45nm node low cost - general purpose applications
2005 · F. Boeuf, F. Arnaud, et al. · Symposium on VLSI Technology · 16
65nm LP/GP mix low cost platform for multi-media wireless and consumer applications
2005 · B. Tavel, B. Duriez, et al. · European Solid-State Device Research Conference · 16
Laser-annealed junctions with advanced CMOS gate stacks for 32nm Node: Perspectives on device performance and manufacturability
2008 · C. Ortolland, T. Noda, et al. · Symposium on VLSI Technology · 15
Migrating from planar to FinFET for further CMOS scaling: SOI or Bulk?
2009 · T. Chiarella, L. Witters, et al. · European Solid-State Device Research Conference · 14
Layout Scaling of $\hbox{Si}_{1-x}\hbox{Ge}_{x} \hbox{-Channel}$ pFETs
2011 · Geert Eneman, Shinpei Yamaguchi, et al. · IEEE Transactions on Electron Devices · 13
Ion-implantation-based low-cost Hk/MG process for CMOS low-power application
2010 · C. Ortolland, S. Sahhaf, et al. · Symposium on VLSI Technology · 13
Optimized ultra-low thermal budget process flow for advanced High-K / Metal gate first CMOS using laser-annealing technology
2006 · C. Ortolland, L.-Å. Ragnarsson, et al. · Symposium on VLSI Technology · 13
High-mobility Si1−xGex-channel PFETs: Layout dependence and enhanced scalability, demonstrating 90% performance boost at narrow widths
2010 · G. Eneman, S. Yamaguchi, et al. · Symposium on VLSI Technology · 12
Cap layer and multi-work-function tuning impact on TDDB/BTI in SOI FinFET devices
2018 · Wen Liu, Andreas Kerber, et al. · IEEE International Reliability Physics Symposium proceedings · 11
Mechanisms of stress generation within a polysilicon gate for nMOSFET performance enhancement
2006 · Pierre Morin, Claude Ortolland, et al. · Materials Science and Engineering B · 11
Analysis of pocket profile deactivation and its impact on Vth variation for Laser annealed device using an atomistic kinetic Monte Carlo approach
2010 · T. Noda, W. Vandervorst, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 10
On the ‘permanent’ component of NBTI
2010 · T. Grasser, Th. Aichinger, et al. · IEEE International Integrated Reliability Workshop final report · 10
Strain enhanced low-VT CMOS featuring La/Al-doped HfSiO/TaC and 10ps invertor delay
2008 · S. Kubicek, T. Schram, et al. · Symposium on VLSI Technology · 10
New carbon-based thermal stability improvement technique for NiPtSi used in CMOS technology
2010 · C. Ortolland, M. Togo, et al. · Microelectronic Engineering · 9
Laser annealed junctions: Pocket profile analysis using an atomistic kinetic Monte Carlo approach
2010 · T. Noda, C. Ortolland, et al. · Symposium on VLSI Technology · 9
Works count: 52
Citation count: 727
H-index: 14
I10-index: 23
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