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Michael P. Duane

Observed names: M. Duane, M. P. Duane, M.P. Duane, MICHAEL P. DUANE, Michael Duane
OpenAlex ID: A5111613469
APF pitch-halving for 22nm logic cells using gridded design rules
2008 · Michael C. Smayling, Christopher Bencher, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 30
A highly integrated 65-nm SoC process with enhanced power/performance of digital and analog circuits
2012 · L. T. Clark, D. Zhao, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 23
Lightly doped drain transistors for advanced VLSI circuits
1985 · D.A. Baglee, C. Duvvury, et al. · IEEE Transactions on Electron Devices · 19
Basic science and challenges in process simulation
2007 · J. Dąbrowski, H.-J. Müssig, et al. · Advances in Solid State Physics · 16
An analytical method for determining intrinsic drain/source resistance of lightly doped drain (LDD) devices
1984 · Charvaka Duvvury, Dave Baglee, et al. · Solid-State Electronics · 15
Series resistance modeling for optimum design of LDD transistors
1983 · C. Duvvury, D.A. Baglee, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 14
Dopant profile control and metrology requirements for sub-0.5 μm metal–oxide–semiconductor field-effect transistors
1996 · Michael Duane, Peter Nunan, et al. · Journal of Vacuum Science & Technology B Microelectronics and Nanometer Structures Processing Measurement and Phenomena · 13
TCAD Needs and Applications from a User's Perspective
1999 · Michael Duane · IEICE Transactions on Electronics · 10
The Role of TCAD in Compact Modeling
2002 · Michael Duane · TechConnect Briefs · 5
Metal–oxide–semiconductor field-effect transistor junction requirements
1998 · Michael Duane, William Lynch · Journal of Vacuum Science & Technology B Microelectronics and Nanometer Structures Processing Measurement and Phenomena · 5
Scaled LOCOS Processes with Reduced Narrow Width Effects
1984 · David A. Baglee, Michael C. Smayling, et al. · Japanese Journal of Applied Physics · 5
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Optimization of P+/N junction formation using solid phase epitaxy for the 100 nm technology node and beyond
2002 · H. Graoui, A. Al-Bayati, et al. · International Conference on Ion Implantation Technology · 4
Comments on "Source-and-drain series resistance of LDD MOSFET's"
1984 · C. Duvvury, D.A.G. Baglee, et al. · IEEE Electron Device Letters · 4
ALTA 4700 system mask patterning performance improvements for X-architecture and wafer electrical performance interchangeability with 50kV E-beam
2005 · Paul C. Allen, Mike Bohan, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 3
Controlling mesh effects in integrated process and device simulation
2002 · V. Axelrad, M. Duane · International Workshop on Statistical Metrology (IWSM) · 2
Improved p-ch MOS transistor performance with an arsenic supersteep retrograde channel profile
1999 · James F. Buller, Jon Cheek, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 1
Re-examination of 2D dopant profiling needs
1998 · Michael Duane · International Conference on Characterization and Metrology for ULSI Technology · 1
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Scaling Gate Electrode Thickness for 0.18 μm CMOS Devices
1994 · Peter Nunan, Kin P. Cheung, et al. · European Solid-State Device Research Conference · 1
Accelerating yield ramp through design and manufacturing collaboration
2004 · Robin C. Sarma, Huixiong Dai, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE
Taking the X Architecture to the 65-nm technology node
2004 · Robin C. Sarma, Michael C. Smayling, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE
Manufacturability of the X Architecture at the 90-nm technology node
2004 · Michael C. Smayling, Robin C. Sarma, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE
Quantitative two-dimensional profiling of 0.35 μm transistors with lightly doped drain structures
2000 · A. McDonald, R. Mahaffy, et al. · Journal of Vacuum Science & Technology B Microelectronics and Nanometer Structures Processing Measurement and Phenomena
Line length dependencies in interconnect optimization
1997 · Daniel Kadoch, Michael Duane, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE
Device performance and optimization for 5th- and 6th-generation microprocessors
1997 · Bijnan Bandyopadhyay, Jon Cheek, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE
Reduced narrow-width effects in a scaled local oxidation of silicon process
1985 · David A. Baglee, M. P. Duane, et al. · Canadian Journal of Physics
Works count: 27
Citation count: 171
H-index: 8
I10-index: 8
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