Author

Seung-Ho Pyi

Observed names: SeungHo Pyi, Seungho Pyi

Institution: SK Hynix (South Korea)

Observed institutions: SK Group (United States), SK Hynix (South Korea)

OpenAlex ID: A5111970964

Inherent Issues and Challenges of Program Disturbance of 3D NAND Flash Cell

2012 · Keon-Soo Shim, Eun-Seok Choi, et al. · IEEE International Memory Workshop (IMW) · 30

Advanced DC-SF Cell Technology for 3-D NAND Flash

2013 · Seiichi Aritome, Yoohyun Noh, et al. · IEEE Transactions on Electron Devices · 25

A New Metal Control Gate Last process (MCGL process) for high performance DC-SF (Dual Control gate with Surrounding Floating gate) 3D NAND flash memory

2012 · Yoohyun Noh, Youngsoo Ahn, et al. · Symposium on VLSI Technology · 24

Roles of sidewall oxidation in the devices with shallow trench isolation

1999 · Seung-Ho Pyi, In-Seok Yeo, et al. · IEEE Electron Device Letters · 23

Characterizations of Pulsed Chemical Vapor Deposited-Tungsten Thin Films for Ultrahigh Aspect Ratio W-Plug Process

2005 · Soo-Hyun Kim, Eui-Sung Hwang, et al. · Journal of The Electrochemical Society · 20

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Modeling and Characterization of Program / Erasure Speed and Retention of TiN-gate MANOS (Si-Oxide-SiNx-Al2O3-Metal Gate) Cells for NAND Flash Memory

2007 · Eun-Seok Choi, Hyun-Seung Yoo, et al. · IEEE International Memory Workshop (IMW) · 14

Pulsed CVD of Tungsten Thin Film as a Nucleation Layer for Tungsten Plug-Fill

2004 · Soo-Hyun Kim, Eui-Sung Hwang, et al. · Electrochemical and Solid-State Letters · 14

How to minimize CD variation and overlay degradation induced by film stress

2012 · Woo-Yung Jung, Yong-Hyun Lim, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 8

Roles of Ti, TiN, and WN as an Interdiffusion Barrier for Tungsten Dual Polygate Stack in Memory Devices

2007 · Min Gyu Sung, Kwan-Yong Lim, et al. · Japanese Journal of Applied Physics · 8

CVD-cobalt for low resistance word line electrode of 3D NAND flash memory

2011 · MinSoo Kim, SungJin Whang, et al. · IEEE International Interconnect Technology Conference (IITC) · 7

Observation of Micro-Oxygen Precipitates in the Vicinity of the Oxidation-Induced Stacking Fault Ring and Their Effects on Thin Gate Oxide Breakdown

2001 · Hyun-Soo Kim, Ki-Sang Lee, et al. · Japanese Journal of Applied Physics · 6

Influence of Hydrogen Incorporation on the Reliability of Gate Oxide Formed by Using Low-Temperature Plasma Selective Oxidation Applicable to Sub-50-nm W-Polymetal Gate Devices

2008 · Kwan-Yong Lim, Min-Gyu Sung, et al. · IEEE Electron Device Letters · 3

Incorporation Effect of Thin Al2O3 Layers on ZrO2–Al2O3 Nanolaminates in a Composite Oxide–High-κ-Oxide Stack for Floating-Gate Flash Memory Devices

2007 · Moon Sig Joo, Seung Ryong Lee, et al. · Japanese Journal of Applied Physics · 2

Study of Plasma Damage at Recess-Channel Gate (RG) Structure During Plasma Nitridation

2007 · Heung-Jae Cho, Tae-Yoon Kim, et al. · IEEE International Reliability Physics Symposium proceedings · 1

Low resistive tungsten dual polymetal gate process for high speed and high density memory devices

2007 · Yong Soo Kim, Kwan-Yong Lim, et al. · European Solid-State Device Research Conference · 1

The incorporation effect of thin Al2O3 layers on ZrO2-Al2O3 nanolaminates in the composite oxide-high-K-oxide stack for the floating gate flash memory devices

2007 · Moon Sig Joo, Seung Ryong Lee, et al. · International Conference on Solid State Devices and Materials (SSDM)

Diffusion Barrier Characteristics of TiSix/TiN for Tungsten Dual Poly Gate in DRAM

2007 · Min Gyu Sung, Kwan-Yong Lim, et al. · International Conference on Solid State Devices and Materials (SSDM)

The incorporation effect of thin Al_2O_3 layers on ZrO_2-Al_2O_3 nanolaminates in the composite oxide-high-K-oxide stack for the floating gate flash memory devices

2006 · Joo Moon Sig, Lee Seung Ryong, et al.

Sidewall oxidation behavior of dichlorosilane-based W-polycide gate

2001 · Hyeon-Soo Kim, Sang-Moo Lee, et al. · Journal of Vacuum Science & Technology B Microelectronics and Nanometer Structures Processing Measurement and Phenomena

Double Spacer LOCOS Process with Shallow Recess of Silicon for 0.20 μm Isolation

1996 · Byung-Jin Cho, Se-Aug Jang, et al. · International Conference on Solid State Devices and Materials (SSDM)

Works count: 20

Citation count: 186

H-index: 8

I10-index: 7