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M. Ueki

Low-power embedded ReRAM technology for IoT applications
2015 · M. Ueki, K. Takeuchi, et al. · Symposium on VLSI Technology · 70
45-nm gate length CMOS technology and beyond using steep halo
2002 · H. Wakabayashi, M. Ueki, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 39
Sub-50-nm physical gate length CMOS technology and beyond using steep halo
2002 · H. Wakabayashi, M. Ueki, et al. · IEEE Transactions on Electron Devices · 38
Low-power embedded ReRAM technology for IoT applications
2015 · M. Ueki, K. T. Akeuchi, et al. · Symposium on VLSI Circuits · 35
Effects of Ti Addition on Via Reliability in Cu Dual Damascene Interconnects
2004 · M. Ueki, M. Hiroi, et al. · IEEE Transactions on Electron Devices · 24
Comprehensive Chemistry Designs in Porous SiOCH Film Stacks and Plasma Etching Gases for Damageless Cu Interconnects in Advanced ULSI Devices
2008 · Y. Hayashi, H. Ohtake, et al. · IEEE Transactions on Semiconductor Manufacturing · 21
Highly-oriented PVD Ruthenium Liner for Low-resistance Direct-plated Cu Interconnects
2007 · M. Abe, M. Ueki, et al. · IEEE International Interconnect Technology Conference (IITC) · 14
Robust porous SiOCH/Cu interconnects with ultrathin sidewall protection liners
2006 · M. Tada, T. Tamura, et al. · IEEE Transactions on Electron Devices · 13
3D stacked CIS compatible 40nm embedded STT-MRAM for buffer memory
2021 · M. Oka, Yoshiharu Namba, et al. · 11
Robust Cu Dual Damascene Interconnects With Porous SiOCH Films Fabricated by Low-Damage Multi-Hard-Mask Etching Technology
2006 · H. Ohtake, M. Tagami, et al. · IEEE Transactions on Semiconductor Manufacturing · 11
Highly reliable, 65 nm-node Cu dual damascene interconnects with full porous-SiOCH (k=2.5) films for low-power ASICs
2004 · M. Ueki, M. Narihiro, et al. · Symposium on VLSI Technology · 11
A 65nm-node, Cu interconnect technology using porous SiOCH film (k=2.5) covered with ultra-thin, low-k pore seal (k=2.7)
2004 · M. Tada, Y. Harada, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 9
Suppression of stress induced open failures between via and Cu wide line by inserting Ti layer under Ta/TaN barrier
2003 · M. Ueki, M. Hiroi, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 9
45nm-node Interconnects with Porous SiOCH-Stacks, Tolerant of Low-Cost Packaging Applications
2007 · N. Inoue, M. Tagami, et al. · IEEE International Interconnect Technology Conference (IITC) · 8
High-Performance Cu-Interconnects with Novel Seamless Low-k SiOCH Stacks (SEALS) Featured by Compositional Modulation Process for 45nm-Node ULSI Devices
2006 · M. Tagami, H. Ohtake, et al. · Symposium on VLSI Technology · 7
A metallurgical prescription for electromigration (EM) reliability improvment in scaled-down, Cu dual damascene interconnects
2006 · M. Tada, M. Abe, et al. · IEEE International Interconnect Technology Conference (IITC) · 6
Plasma Co-polymerization Technology with Molecular-level Structure Tightening in "In-situ" SiOCH Stacks for 32nm-node Cu Interconnects
2006 · M. Tada, H. Yamamoto, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 6
High performance Cu interconnects with damage-less full molecular-pore-stack (MPS) SiOCH for 32nm-node LSIs and beyond
2008 · M. Ueki, M. Tagami, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 4
Cost-effective and High Performance Cu Interconnects (keff=2.75) with Continuous SiOCH Stack Incorporating a Low-k Barrier Cap (k=3.1)
2007 · M. Ueki, H. Yamamoto, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 4
Effects of metal-cap coverage on electro-migration (EM) tolerance for scaled-down Cu interconnects
2011 · M. Ueki, E. Nakazawa, et al. · IEEE International Interconnect Technology Conference (IITC) · 2
Robust low-k film with sub-nm pores and high carbon content for highly reliable Cu/low-k BEOL modules
2012 · N. Inoue, M. Tagami, et al. · IEEE International Interconnect Technology Conference (IITC) · 1
Path-finding for integration of porous SiOCH films (k∼2.5) in system-LSIs
2010 · N. Inoue, M. Ueki, et al. · IEEE International Interconnect Technology Conference (IITC) · 1
RF performance boosting for 40nm-node CMOS device by low-k/Cu dual damascene contact
2008 · J. Kawahara, K. Hijioka, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 1
A new direct low-k/Cu dual damascene (DD) contact lines for low-loss (LL) CMOS device platforms
2008 · J. Kawahara, M. Ueki, et al. · Symposium on VLSI Technology · 1
Suppression of Cu Ion Drift by Metal-Cap on Cu lines, Improving Interconnect Dielectric Reliability
2014 · M. Ueki, N. Furutake, et al. · International Conference on Solid State Devices and Materials (SSDM)
Works count: 31
Citation count: 346
H-index: 11
I10-index: 11
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